1. Field of the Invention
The present invention relates to a driving circuit applied to a display system, and more particularly, to a driving with a protecting circuit to limit a high voltage surge introduced by parasitic inductance, driving method and associated display system.
2. Description of the Prior Art
Refer to FIG. 1, which is a diagram illustrating a display system 100 in the prior art. As shown in FIG. 1, the display system 100 comprises a plurality of Light-Emitting Diodes (LED) D1 to DN, a plurality of nodes N1 to NN, a plurality of transistors M1 to MN, and a plurality of current sources I1 and IN, wherein the transistors M1 to MN are controlled to be opened or closed by a plurality of Pulse Width Modulation (PWM) signals Ven1 to VenN. The states of the transistors M1 to MN change between open and close constantly by referring to the PWM signals Ven1 to VenN to make the states of the LEDs D1 to DN change between light-on and light-off constantly, and the average luminance of LEDs D1 to DN are decided according to the time ratio of light-on state and light-off state of the LEDs D1 to DN (i.e. the duty cycles of the PWM signals Ven1 to VenN).
Refer to FIG. 2, which is an ideal waveform illustrating a voltage of the node N1 and a current of the LED D1 when the PWM signal Ven1 changes to low level from the high level. As shown in FIG. 2, when the PWM signal Ven1 is on high level (e.g. 3V shown in FIG. 2), the transistor M1 is conductive to make the LED D1 have a current and illuminate. In this time, the voltage level of the node N1 is 0V. Next, when the PWM signal Ven1 decreases to 0V from 3V, the current of the LED D1 decreases to OA due to the transistor M1 is non-conductive (i.e. the LED D1 does not illuminate). In this time, the voltage level of the node N1 equals to a supple voltage VLED of the LED D1 (e.g. 5V shown in FIG. 2).
However, because when the PWM signal Ven1 decreases to low level from the high level to close the transistor M1, there is a parasitic inductance between the node N1 and the LED D1, therefore, the node N1 has a very high voltage surge and damages the circuit. FIG. 3 is a practical waveform illustrates the voltage of the node N1 and the current of the LED D1 when the PWM signal Ven1 changes to low level from high level. As shown in FIG. 3, the PWM signal Ven1 decreases to 0V from 3V, the voltage level of the node N1 suddenly jumps to a level close to 25V, in this way, the adjacent circuit of the node N1 might be damaged and influences the circuit. In addition, with the increase of the frequency of the PWM signal Ven1, the above-mentioned voltage surge phenomenon might be more serious.